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Network-on-Chip
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.
Artificial Plasmonics for VLSI Interconnects
Build the microchips of the future with this revolutionary new information transfer technology Advancements in high-performance computing have continually demanded for progresses in disruptive technological research and innovations. Moore's Law has pushed the Very Large Scale Integration (VLSI) technology to pack MOS devices inside a chip at an exponential rate, thereby surpassing now eight billion transistors per cm2. This has concomitantly fueled the growth of multilayered on-chip interconnects comprising metallic and low dielectric materials. VLSI Interconnect Technology with Artificial Plasmonics introduces a new method for improving chip performance by harnessing the power of informatio...
