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Formal Modeling and Analysis of Timed Systems
This book constitutes the thoroughly refereed post-proceedings of the First International Workshop on Formal Modeling and Analysis of Timed Systems, FORMATS 2003, held in Marseille, France in September 2003. The 19 revised full papers presented together with an invited paper and the abstracts of two invited talks were carefully selected from 36 submissions during two rounds of reviewing and improvement. All current aspects of formal method for modeling and analyzing timed systems are addressed; among the timed systems dealt with are timed automata, timed Petri nets, max-plus algebras, real-time systems, discrete time systems, timed languages, and real-time operating systems.
Automated Technology for Verification and Analysis
This book constitutes the refereed proceedings of the Second International Conference on Automated Technology for Verificaton and Analysis, ATVA 2004, held in Taipei, Taiwan in October/November 2004. The 24 revised full papers presented together with abstracts of 6 invited presentations and 7 special track papers were carefully reviewed and selected from 69 submissions. Among the topics addressed are model-checking theory, theorem-proving theory, state-space reduction techniques, languages in automated verification, parametric analysis, optimization, formal performance analysis, real-time systems, embedded systems, infinite-state systems, Petri nets, UML, synthesis, and tools.
Computer Aided Verification
This volume contains the proceedings of the conference on Computer Aided V- i?cation (CAV 2002), held in Copenhagen, Denmark on July 27-31, 2002. CAV 2002 was the 14th in a series of conferences dedicated to the advancement of the theory and practice of computer-assisted formal analysis methods for software and hardware systems. The conference covers the spectrum from theoretical - sults to concrete applications, with an emphasis on practical veri?cation tools, including algorithms and techniques needed for their implementation. The c- ference has traditionally drawn contributions from researchers as well as prac- tioners in both academia and industry. This year we received 94 regular paper submissions out of which 35 were selected. Each submission received an average of 4 referee reviews. In addition, the CAV program contained 11 tool presentations selected from 16 submissions. For each tool presentation, a demo was given at the conference. The large number of tool submissions and presentations testi?es to the liveliness of the ?eld and its applied ?avor.
Computer Aided Verification
This book constitutes the refereed proceedings of the 13th International Conference on Computer Aided Verification, CAV 2001, held in Paris, France in July 2001. The 33 revised full papers presented were carefully reviewed and selected from 106 regular paper submissions; also included are 13 reviewed tool presentations selected from 27 submissions. The book offers topical sections on model checking and theorem proving, automata techniques, verification core technology, BDD and decision trees, abstraction and refinement, combinations, infinite state systems, temporal logics and verification, microprocessor verification and cache coherence, SAT and applications, and timed automata.
Advances in Verification of Time Petri Nets and Timed Automata
This monograph presents a comprehensive introduction to timed automata (TA) and time Petri nets (TPNs) which belong to the most widely used models of real-time systems. Some of the existing methods of translating time Petri nets to timed automata are presented, with a focus on the translations that correspond to the semantics of time Petri nets, associating clocks with various components of the nets. "Advances in Verification of Time Petri Nets and Timed Automata – A Temporal Logic Approach" introduces timed and untimed temporal specification languages and gives model abstraction methods based on state class approaches for TPNs and on partition refinement for TA. Moreover, the monograph presents a recent progress in the development of two model checking methods, based on either exploiting abstract state spaces or on application of SAT-based symbolic techniques. The book addresses research scientists as well as graduate and PhD students in computer science, logics, and engineering of real time systems.
Proceedings
The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the World, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. ATS 2003's papers shares state-of-the-art ideas and technologies in testing.
